In the area of memories, dynamic random access memories (DRAMs) typically perform as the main memory of a computer system. That is, in a typical computer system, such as a desk top personal computer (PC), the main memory function is performed by DRAM devices. The operation of a DRAM generally entails the use of row and column addresses for addressing the memory, so that read and write operations may be performed on the DRAM components. It is appreciated that in many instances, DRAMs are utilized with a processor, such as a central processing unit of a computer, but in other instances, the DRAM may be used with other processing/controlling devices, such as memory controllers.
In order to provide much higher performance in faster computer systems, higher performance requirements are also placed on DRAMs to process data in much larger quantities and in much faster performance time. Thus, it is not uncommon to find DRAMs configured into banks of DRAM arrays, in which data transfer to and from the DRAM arrays are achieved by high data speed bursts. For example, a high-speed 256 mega bit (Mb) DRAM, arranged in multiple banks, may be clocked to provided data transfer with an issuance of a read and/or write access command. In one such configuration, it may be possible to provide a specialized clocked signal (referred to as a flag signal) to trigger the data transfer in response to the read or write access to the DRAM. In some instances, the data transfer may be effected with both the rising and falling transitions of the flag signal. For example, a first read/write access may be triggered on a rising transition of such a flag signal, while a second read/write access may be triggered in response to the falling transition of the flag signal. This data transfer to/from the DRAM at both the rising and falling transitions of the flag signal may allow two memory accesses in response to one cycle of the flag signal. For example, such a scheme may be implemented so that data transfer to/from one portion of the memory may be achieved in response to the rising transition of the flag signal and a second data transfer occurs to/from another portion of the memory in response to the falling transition of the clock signal.
However, in order to implement this scheme, a memory accessing protocol may require the use of four separate memory commands to perform the read and write accesses. For example, two commands (read on rising transition and read on falling transition) may be required to perform the read accesses at both transitions. Likewise, two write commands (write on rising transition and write on falling transition) may be required to perform write accesses at both transitions. Thus, four separate read/write commands may be required to ensure that the correct DRAM device transmits or receives the correct corresponding data. Although four separate read/write commands may be implemented in a DRAM accessing scheme, supporting four such different read and write commands may introduce complexity in the command structure. Having two additional commands may also detract from an ability to add other commands due to a limitation on the pin connections available on the DRAM device. An alternative is to have a DRAM controlling scheme in which only one read command and one write command control data transfers to/from the DRAM, but in which data transfers are effected at both rising and falling transitions of flag signal. By reducing the number of command encodings for read and write commands to two, it may be possible to simplify the memory controller command encodings and, further, reduce the pin count of DRAM devices (or, alternatively, to use the additional pins for other signals).